Senior Design Verification Engineer - #1684533

We've partnered with an exciting AI start-up that is solving the AI compute problem by developing photonics-based interconnects.

They're hiring a Senior Verification Engineer to help build their verification infrastructure.

Responsibilities

• Implement verification infrastructure and test cases in collaboration with the design team and external partners.


• Debug failures, create and track issues to resolution.


• Develop and maintain automated regression test infrastructure and gatekeepers.

Requirements

• Deep expertise in industry-standard verification methodologies, including proficiency with SystemVerilog and UVM.


• Ability to think creatively about solutions outside of UVM.


• Experience with high-speed networking interfaces and protocols like PCIe, SERDES or Ethernet.


• Demonstrated ability to collaborate effectively with design teams to meet objectives.

If you'd like more information, apply below!